Equipment for displaying and recording/reproducing video signals, such as TVs and videotape recorders (VTRs), performs signal processing based on sync signals superimposed on the video signals in their blanking intervals. Therefore, to ensure stable display and recording/reproduction, it is required to separate sync signals invariably stably, irrespective of the quality of input video signals. Japanese Laid-Open Patent Publication No. 01-71280, for example, discloses that stabilization of a separated horizontal sync signal is improved by using a horizontal sync signal generated by an automatic frequency control (AFC) circuit, which is free from excessive or missing synchronizing pulses, in place of the separated horizontal sync signal itself.
As for stabilization of a vertical sync signal, also, an example using an AFC circuit is disclosed in Japanese Laid-Open Patent Publication No. 4-188960. FIG. 23 is a block diagram of such a conventional vertical sync signal generator.
Referring to FIG. 23, a sync signal separation circuit 91 receives a video signal including a luminance signal, separates a vertical sync signal from the video signal, and outputs the separated signal to an AFC circuit 92 and a vertical sync signal detection circuit 93. The AFC circuit 92 and a FvVCO circuit 94 constitute a phase locked loop (PLL) having a feedback loop. The AFC circuit 92 compares the phase of the vertical sync signal separated by the sync signal separation circuit 91 with the phase of a signal output from the FvVCO circuit 94, and outputs the resultant phase error to the FvVCO circuit 94. The FvVCO circuit 94 changes its oscillating frequency according to the phase error and outputs a signal having a frequency equal to the vertical frequency. Therefore, a frequency-stabilized signal can be output from the FvVCO circuit 94 even if the vertical sync signal separated by the sync signal separation circuit 91 has excessive or missing synchronizing pulses.
The vertical sync signal detection circuit 93 detects existence/absence of a vertical sync signal and outputs the result to a selector 96 as a selection signal. A FvOSC circuit 95 oscillates in free-run operation, and the output thereof has a frequency stabilized at the vertical frequency. The FvOSC circuit 95 outputs the generated signal to the selector 96. The selector 96 selects one of the outputs of the FvVCO circuit 94 and the FvOSC circuit 95 based on the output of the vertical sync signal detection circuit 93, and outputs the result as the vertical sync signal.
That is, the selector 96 selects and outputs the PLL-stabilized output of the FvVCO circuit 94 when a vertical sync signal in the video signal is detected by the vertical sync signal detection circuit 93. When no vertical sync signal is detected, the selector 96 selects and outputs the output of the FvOSC circuit 95 stably oscillating in free-run operation.
Problem to be Solved
In the configuration described above, switching is made between the signal synchronizing with the vertical sync signal of the input video signal and the signal output from the circuit oscillating in free-run operation, according to existence/absence of a vertical sync signal in the input video signal. Therefore, immediately after the switching, the pulse interval of the vertical sync signal loses continuity, causing synchronization disorder.
In still reproduction in a VTR, for example, the input video signal includes a vertical sync signal, but the vertical sync signal has periods changing alternately every field. When such a video signal is input, the selector 96 selects and outputs the output of the FvVCO circuit 94. Since the PLL averages the frequency of the vertical sync signal of the input video signal, the output of the FvVCO circuit 94 goes out of synchronization with the input video signal.